1. Field of the Invention
The present invention generally relates to integrated circuit memory arrays and more particularly to automatically removing shorted bitlines and wordlines from the memory arrays.
2. Description of the Related Art
A "cross fail" is defined as a low resistance leakage path between two lines in an integrated circuit, such as a wordline and a bitline in a memory array. Undesirably large current may be drawn from the voltage supply to ground when a cross fail occurs. For example, in 64 M dynamic random access memory (DRAM) design, each cross fail could increase stand-by current by as much as 300 mA. In order to limit the current flow, a current limiter device such as a depletion mode-N type field effect transistor (NFET) device has conventionally been used.
FIG. 1 illustrates a schematic circuit diagram including bitlines 10, a wordline 11, an equalization control (EQ) line 12, an equalization voltage supply (Vbleq) line 13, a current limiter (e.g., depletion mode device) 14, a wordline driver 16, and a short 15 between one of the bitlines 10 and the wordline 11.
However, the introduction of the depletion device 14, as shown in FIG. 1, increases the chip area and process complexity. For example, such a structure would require an extra threshold voltage (Vt) implant. Additionally, the depletion device itself often degrades performance during the array precharge operation. Thus, the conventional structure shown in FIG. 1, often equalizes bitlines at a level that is different from the predetermined value of Vbleq, which weakens the precharge capability. Such weak precharge capability causes an asymmetric signal sensing margin and finally results in poor sensing speed.
The invention overcomes the conventional problems by removing shorts 15 between the bitlines 10 and wordline 11 without requiring a current limiter 14 as in the conventional structures. Therefore, by eliminating the current limiter 14, the invention avoids the foregoing disadvantages.